OVPsim beats QEMU in fidelity in CPU simulation - its determinism and speed were pretty impressive. OVPsim configurability is a big advantage as well. We were able to configure low-level CPU features, thanks to comprehensive documentation. I was also enthusiastic about the machine description file. It was easy to connect a missing interrupt signal we needed.

The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores.  The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.

The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.