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OpenHW TV Episode 1: RISC-V Processor Verification

The first episode of OpenHW TV focused on the Verification of CORE-V open source RISC-V processor IP cores. Guests include the new Co-Chairs of the OpenHW verification task group (Futurewei and SiliconLabs) with contributing members Imperas Software and Metrics Technologies highlighting the open CORE-V processor IP Design Verification (DV) plan using state of the art flows and SystemVerilog UVM testbenches with encapsulated Imperas RISC-V reference model, coverage-based flow, and Metrics flexible cloud-based environment. Includes a Q&A session after the updates and presentations.

The video can be viewed here.

 

Comments

  • Josh Scheid, Head of Design Verification

    Ventana Micro Systems Inc

    At Ventana, our teams of developers are building the foundational processor IP and chiplet building blocks that will enable a step change in performance for the most demanding compute workload markets.

    Our verification strategy is to exercise the RISC-V based processors across the most demanding scenarios and are using Imperas RISC-V vector test suites in addition to the Imperas golden reference model in our verification environment.

  • G. S. Madhusudan, CEO

    InCore

    RISC-V momentum and interest is wide-ranging across academic and industry. In providing support for the IIT Madras Shakti processors, InCore sees an increasing attention to test and verification that will be supported with riscvOVPsim.