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OpenHW and verification of RISC-V Open ISA cores

OpenHW presentation on "Verification of Open RISC-V cores: Adding value to the CORE-V Family of open source processor cores" by Mike Thompson, Director of Engineering, Verification Task Group at OpenHW Group, at the RISC-V pavilion during the virtual event for DAC 2020.

While open source processor IP cores have some attractive qualities, concerns on verification remain a key barrier to adoption. At OpenHW group the members and supporters are addressing the verification of the CORE-V family of open source processor cores using industry standard tools and flows.

This talk with share the details of the SystemVerilog UVM methodologies based on a reference model encapsulation for step-and-compare testing, and the use of the open source Google Instruction Stream Generator. With the latest coverage results and analysis, this talk will highlight the process within the Verification Working group with co-chairs supported by Futurewei Technologies, Inc. and Silicon Labs.


This DAC presentation can be viewed on the YouTube channel for DAC TV here.