Simulating Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux
This short video shows the Imperas OVP model of the RISC-V Andes N25 core running FreeRTOS in a heterogeneous platform with an Imperas OVP model of an ARM Cortex-15MPx4 core booting SMP Linux.
Comments
Mike Ingster, President and Founder
Quantum Leap Sales
Imperas solutions for early software development have never been more appropriate with development schedules more critical than ever. We believe that simulation-based verification is fast becoming an essential requirement in complex SoCs, and together with advanced debug and analysis tools for many-core and heterogeneous designs will greatly reduce development schedules for next generation devices.
Premal Buch, VP Software
Altera
Given the wide variety of customer applications for our SoC FPGAs, our software stacks require rigorous and comprehensive testing. Imperas' M*SDK has proven to be an outstanding environment for the validation and analysis of operating systems, drivers and firmware. Verification using the Imperas solution not only accelerates software bug discovery, but also provides a rapid understanding of the root cause of problems.