Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Imperas Golden RISC-V Reference Model helped us find many bugs in our cores.
However, the RISC-V architectural tests yielded no bugs, which is expected since the architectural tests are a subset of full verification.
Shlomit Weiss, Senior VP of Silicon Engineering
Mellanox Technologies
We have selected Imperas simulation tools and RISC-V models for our design verification flow because of the quality of the models and the ease of use of the Imperas environment.
Imperas reference model of the complete RISC-V specification, the ability to add our custom instructions to the model and their experience with processor RTL DV flows were also important to our decision.