Wei Wu, Vice-Chair of RISC-V International P Extension Task Group
PLCT Lab, ISCAS.
By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency.
The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.
Sebastian Ahmed, Senior Director of R&D
Silicon Labs
Silicon Labs selected Imperas simulation tools and RISC-V models for our design verification (DV) flow because of the quality of the models and the ease of use of the Imperas environment.
The Imperas golden reference model of the RISC-V core and their experience with processor RTL DV flows were also critical to our decision.