For the automotive market our customers expect the highest standards of quality and design assurance. NSITEXE selected the Imperas Vector Extensions Compliance test cases and RISC-V Reference Model as a foundation for our simulation-based design verification (DV) plans.
Arjan Bink, chair of OpenHW Cores Task Group
Silicon Laboratories
High quality IP is an important deliverable that others can build on, but developers need more than just processor RTL to support high quality implementations.
All embedded software is closely related to the IP core it will run on; thus, an accurate ISS reference model is essential for all HW and SW adopters. riscvOVPsimCOREV is the key starting point for the support of the OpenHW CORE-V cores by the ecosystem.