Melaine Facon, Director of Codasip’s French Design Centre
Codasip
An open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects.
With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.
Simon Davidmann, Founder & CEO
Imperas Software
We are proud to extend our long-standing relationship with Andes, and now announce Andes certification of our OVP models for their 32-bit/64-bit CPU cores, as a reference simulator.