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Imperas at Korea RISC-V Summit, September 21st 2020

Imperas certified design partner Coontec will be participating with a presentation and panel discussion on the latest developments around RISC-V in Korea

Korea RISC-V Summit 2020 - Coontec & Imperas

 

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their certified design partner Coontec will be participating at the Korea RISC-V Summit 2020 with presentations and a panel discussion on the latest development and potential for RISC-V in Korea.

 

Presentation ‘Simulation and methodology for verification of RISC-V designs’

  • Speaker:         Joon Pang – CEO of Coontec
  • Co-Author:     Larry Lapides – Imperas Software
  • When:             Monday September 21st 2020

Abstract: As Moore's Law hits its limits, one way to improve application performance is with the optimizations and customizable features of RISC-V. The new paradigm of RISC-V is spreading rapidly and the results are showing success in many application areas. However, the biggest obstacles that open source processors must overcome are ecosystem compatibility and processor design validation. In this talk, Coontec explains the efficient process and methodology for early verification and compliance within the proven design flows used for SoC’s.

  • What:              Korea RISC-V Summit 2020
  • Where:            Korea Broadcasting Center: 233, Mokdong-ro, Yangcheon-gu, Seoul, South Korea
  • When:             Monday September 21st 2020 – 1pm to 5:30pm

 

Registration is available at this link.


 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

ARM TrustZone Platform Modeling Application Note

Comments

  • Allen Baum, Chair of the RISC-V International Architecture Test SIG

    Esperanto Technologies, Inc.

    A key part of the RISC-V privilege specification that is fundamental for OS and application security is the PMP feature.

    Enabling its correct operation is essential for security applications, and the Imperas PMP test suites are a valuable contribution to the RISC-V compatibility and verification community.

  • Alexander Redkin, CEO

    Syntacore

    As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.