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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

How to Address RISC-V Compliance with Open-ISA and Custom Instructions

Abstract:

In December 2018 the RISC-V Foundation held its inaugural Summit in Silicon Valley. Simon Davidmann reviewed several issues for the industry related to an Open Standard ISA and how the many different implementations can be made compliant to the standard. A status of the Foundations compliance test suite is given and information on the Imperas riscvOVPsim compliance simulator and Mutating Fault Simulation Coverage tool is provided. These are the slides presented.

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Comments

  • Sandeep Vij, President and CEO

    MIPS Technologies

    We chose Imperas and the Open Virtual Platform technology because of the quality of the models and technology.  We see the positive momentum and leadership position of OVP, and believe this is the best technology for instruction accurate simulation of processor core models.

  • Dr. Charlie Su, CTO and EVP

    Andes Technology

    All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.

    Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.