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Extending SoC Design Verification Methods for RISC-V Processor DV - Article and video presentation

During the virtual DAC 2020 event Mentor hosted the traditional verification academy talks online.

Imperas presented "Extending SoC Design Verification Methods for RISC-V Processor DV" by Simon Davidmann, CEO at Imperas, at the Mentor Verification Academy event during the virtual event for DAC 2020.

As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established SoC verifications tasks and methods are well proven, yet depend on the industry wide assumption of "known good processor IP". However, the new DV challenges are not purely focused on the processor IP. Since an Open ISA allows much greater design freedom, the impact extends well into the SoC itself. Mentors Questa is fundamental to the RISC V processor verification with the RTL of the processor DUT (Device Under Test) and a RISC-V golden reference model encapsulated in the SystemVerilog UVM testbench allows step-and-compare testing.

This talk outlines the new test methods including instruction stream generators, reference models and SystemVerilog testbenches for Questa and includes results from testing some popular open source RISC-V cores.

The written paper and video can be viewed at the Mentor Verification Horizons site on this link.