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Exploring Next Generation SoC Architectures with Virtual Platforms and RISC-V

Imperas presentation on "Exploring Next Generation SoC Architectures with Virtual Platforms and RISC-V" by Kevin McDermott, VP of Marketing at Imperas, at the SemIsrael Virtual Technology Week 2020, June 15-17 2020.

As SoC designers explore new architectural approaches with multi-processor configuration and arrays, virtual platforms allow rapid design options and support full application software development to fine tune and test new multi-processor structures with development iterations at the speed of software. RISC-V adds new dimensions of processor flexibility with many options and configurations plus custom instructions. Using software driven design methodologies allows profiling and analysis of new extensions for domain specific applications. The new RISC-V vector extension help support complex arithmetic operations required for applications involving linear algebra, such as supercomputers, cryptography, AI, ML and deep learning (DL). As RISC-V processor are adopted within SoCs, the full design verification (DV) process can be supported with SystemVerilog test benches and reference model-based verification, including the latest work with Google Instruction Stream Generator, compliance suite, and directed tests.

The video can be viewed here.