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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Pushing The Limits Of Hardware-Assisted Verification

Demand for big-iron tools is insatiable as complexity continues to grow.

Semiconductor Engineering

 

As semiconductor complexity continues to escalate, so does the reliance on hardware-assisted simulation, emulation, and prototyping.
Since chip design first began, engineers have complained their design goals exceeded the capabilities of the tools. This is especially evident in verification and debug, which continue to dominate the design cycle. Big-iron tooling has enabled design teams to keep pace with growing complexity through a combination of parallelism, more and different processing elements, and the addition of machine learning….
 

To read the full Semiconductor Engineering article by Ann Steffora Mutschler, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project

    ETH Zurich

    RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.

  • Allen Baum, Chair of the RISC-V International Architecture Test SIG

    Esperanto Technologies, Inc.

    The RISC-V open standard ISA offers a compatibility framework, yet has built-in flexibility across the specification envelope.

    The Imperas contribution of new Crypto extension tests is a welcome addition to the trusted test suite portfolio, supporting implementers with verification of their hardware.