Melaine Facon, Director of Codasip’s French Design Centre
Codasip
An open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects.
With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.
Hermann Haslauer, Head of Embedded Software Support Engineering
Palfinger Europe GmbH
Palfinger is the global leader for innovative crane and lifting solutions.
As our embedded development teams develop and implement our roadmap for digitalization and artificial intelligence, the need for software quality testing has never been greater. The TESSY tool together with the Imperas virtual platform simulators and OVP models of Arm processors, are a quality combination that we use as a foundation of our software test and maintenance process.