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Revolutionizing Embedded Software Development

Imperas and Ashling Presentation on Early Software Development Environment for RISC-V at Barcelona Workshop May 2018

Abstract:

At the 8th RISC-V Workshop that was held in Barcelona in May 2018, Imperas and Ashling presented their co-operative work on the use of Virtual Platforms to provide early software development in SoC projects. These are the slides presented.

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Comments

  • Dr. Charlie Su, CTO and EVP

    Andes Technology

    All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.

    Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.

  • Art Swift, VP of Marketing and Business Development

    MIPS Technologies

    We chose Imperas and the Open Virtual Platforms technology because of the quality of the models and technology. We see the positive momentum and leadership position of OVP, and believe this is the best technology for instruction accurate simulation of our processor core models. MIPS Technologies has delivered the first OVP models to lead customers, and we look forward to expanding this program in the future.