RISC-V is a free and open ISA (Instruction Set Architecture) enabling a new era of processor innovation through open standard collaboration. The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. The RISC-V ISA is based on a modular structure with many standard extensions and configuration options, in addition to user defined custom instructions.

The OVP models of the reference standard specification RISC-V cores and platforms are available to download from OVPworld at www.OVPworld.org/ip-vendor-risc-v.

The free enhanced RISC-V ISS, riscvOVPsimPlus package including many test suites and functional coverage analysis is available on OVPWorld at www.OVPworld.org/riscvOVPsimPlus.