Imperas at the 2nd Annual RISC-V Summit, December 2019

Imperas demonstrations include RISC-V Processor Reference Models for hardware verification and the first commercial simulator for RISC-V Vector Extensions

 

RISC-V Summit

 

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, is pleased to be a contributing sponsor for the second annual RISC-V Summit in December in San Jose, California. Imperas will exhibit RISC-V Processor Reference Models for hardware verification and the first commercial simulator for RISC-V Vector Extensions, and RISC-V custom instruction design flows. Imperas conference presentations will focus on RISC-V Processor verification and RISC-V Architecture Exploration for AI & ML Many-core Compute Arrays.

Please contact info@imperas.com to set up a meeting at the RISC-V Summit 2019, or to learn more about Imperas virtual prototyping solutions for embedded software development, debug and test. 

  • What:               RISC-V Summit
  • Where:             San Jose McEnery Convention Center, 150 W San Carlos St, San Jose, CA
  • When:              Conference and Exhibition Dec. 10th & 11th, Tutorials Dec. 12th
  • Agenda:           View the agenda here

 

Register for an Expo or Conference Pass Now with Special Discount Promotion!

Register for the Free Expo-only pass at this link. Or click here to register for the keynotes, conference or tutorial with 25% discount, select the ticket option and press ‘add to basket’ button then enter the VIP code: Imperas.

 

PanelThe RISC-V Open ISA’s shock Wave of Processor Innovation that's Causing a Seismic Shift in SoC Verification Requirements

  • Moderator:      Ann Mutschler, Executive Editor/EDA, Semiconductor Engineering
  • Organizer:       Kevin McDermott, VP Marketing, Imperas Software Ltd.
  • Panelist:          Emerson Hsiao, Senior VP, Andes Technology USA Corp.
  • Panelist:          Dave Kelf, Chief Marketing Officer, Breker Verification Systems
  • Panelist:          Richard Ho, Principal Hardware Engineer, Google, Inc.
  • Panelist:          Frank Schirrmeister, Sr. Group Director (SVG), Cadence Design Systems, Inc.
  • Panelist:          Simon Davidmann, President & CEO, Imperas Software Ltd.
  • Panelist:          Mike Thompson, Director of Verification Engineering, OpenHW Group
  • When:             Tuesday, December 10, 2:20pm

 

PresentationAvoiding Amdahl's Law: RISC-V Architecture Exploration for AI & ML Many-core Compute Arrays

  • Presenter:        Simon Davidmann, President & CEO, Imperas Software Ltd.
  • When:               Tuesday, December 10, 3:40pm

 

PresentationRISC-V Processor Verification based on Open-source Framework and State-of-the-art Cloud-based Methodologies

  • Co-Author:      Lee Moore, Applications Engineer, Imperas Software Ltd.
  • Co-Author:      Richard Ho, Principle Hardware Engineer, Google, Inc.
  • When:              Wednesday, December 11, 3:40pm

 

TutorialRISC-V Verification for Processor Cores and Optional Custom Extensions

  • Co-Author:      Lee Moore, Applications Engineer, Imperas Software Ltd.
  • Co-Author:      Doug Letcher, President & CEO, Metrics Technologies, Inc.
  • Co-Author:      Richard Ho, Principle Hardware Engineer, Google, Inc.
  • When:              Thursday, December 12, 9:00am

 

Exhibit: Stop by the Imperas booth #416 and see all the latest demonstrations and virtual platform technology for RISC-V based designs, including Verification and custom instruction, plus support for the latest RISC-V specifications for Vectors and Bit Manipulation. For more information, or to set up meetings with Imperas at the RISC-V Summit 2019, please contact info@imperas.com.

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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