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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Simulating Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux

This short video shows the Imperas OVP model of the RISC-V Andes N25 core running FreeRTOS in a heterogeneous platform with an Imperas OVP model of an ARM Cortex-15MPx4 core booting SMP Linux.

Comments

  • Mark Himelstein, CTO

    RISC-V International

    RISC-V International’s mission is to support the adoption of RISC-V through industry-wide partnerships and collaboration.

    The continued contributions, including the Imperas Open Source Architecture tests, are helping to ensure an ecosystem of compatibility that all members and users can build on.

  •  Steve Richmond, Co-chair of the OpenHW Group Verification Task Group

    Silicon Laboratories

    Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.

    The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.