Simulating Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux
This short video shows the Imperas OVP model of the RISC-V Andes N25 core running FreeRTOS in a heterogeneous platform with an Imperas OVP model of an ARM Cortex-15MPx4 core booting SMP Linux.
Karel Masarik, CEO and Co-Founder
As RISC-V adoption grows throughout the industry in a variety of application areas, so does the need for robust simulation support from both commercial and open source suppliers. We welcome Imperas' contributions to the rapidly accelerating RISC-V ecosystem.
Mark Himelstein, CTO
RISC-V International’s mission is to support the adoption of RISC-V through industry-wide partnerships and collaboration.
The continued contributions, including the Imperas Open Source Architecture tests, are helping to ensure an ecosystem of compatibility that all members and users can build on.