Simulating Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux
This short video shows the Imperas OVP model of the RISC-V Andes N25 core running FreeRTOS in a heterogeneous platform with an Imperas OVP model of an ARM Cortex-15MPx4 core booting SMP Linux.
Hideki Sugimoto, CTO
New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success.
The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.
Shubhodeep Roy Choudhury, Managing Director & Co-founder
As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve.
Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification