Simulating Andes RISC-V N25 running FreeRTOS and ARM Cortex-A15MPx4 running SMP Linux
This short video shows the Imperas OVP model of the RISC-V Andes N25 core running FreeRTOS in a heterogeneous platform with an Imperas OVP model of an ARM Cortex-15MPx4 core booting SMP Linux.
Shubhodeep Roy Choudhury, Managing Director & Co-founder
Ideally any test should provide a clear pass or fail indication. In the case of RISC-V processor DV this is achieved with a comparison against a quality reference model.
STING helps generate portable, architecturally correct and self-checking tests targeted at the corner-case scenarios by automating the comparison of the DUT against the Imperas reference model results.
CEO of SELTECH Corporation
Imperas enables SELTECH to create new value for our customers by reducing time and cost-to-market, while improving their overall system performance. Our work with market leaders including Imperas and Imagination will help us continue to strengthen our position across the Japanese electronics market and beyond.