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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V at Embedded World 2020: Imperas Presentation

Imperas presentation on "RISC-V Processor Verification and Extensions with Custom Instructions" by Kevin McDermott, VP of Marketing at Imperas, at the RISC-V booth during Embedded World Exhibition and Conference in Nuremberg, Germany.

Covering a range of topics on RISC-V and Imperas contributions to RISC-V with customers, adopters and the ecosystem community. Starting with a brief update and background on Imperas and the RISC-V activities, highlighting the processor models for software development and processor verification, leads on to the work within the Compliance working group including the RV32I suite announced at the RISC-V Summit in December 2019.

Plus, other verification activities based on working with customers on complex RISC-V implementations using the Imperas RISC-V Golden reference model.

The video can be viewed on the RISC-V YouTube channel here.

To see the video directly on YouTube, click here.

 

 

 

Comments

  • Simon Davidmann, Founder and CEO

    Imperas Software

    The new Imperas Embedded Software Development Tool Suite incorporating ToolMorphing technology is already dramatically reducing our customers’ engineering schedules while increasing their product quality.

  • Dr. Charlie Su, CTO and EVP

    Andes Technology

    All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.

    Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.