Decisions about what to run in-house are complex, and may vary from one company to the next.

What’s different about developing code for internet of things (IoT) devices? At one level, not very much. But when you consider what they fit into, the situation looks a lot more complex.
An individual device may perform relatively simple operations but form part of a complex system of systems. Each device needs to be easily…

Decisions about what to run in-house are complex, and may vary from one company to the next.

Discussions about cloud-based EDA tools are heating up for both hardware and software engineering projects, opening the door to vast compute resources that can be scaled up and down as needed.
Still, not everyone is on board with this shift, and even companies that use the cloud don’t necessarily want to use it for every aspect of chip design. But the…

How much value comes from reuse? While still a necessary part of most companies’ methodologies, the advantages are diminishing.

For the past two decades, most designs have been incremental in nature. They heavily leveraged IP used in previous designs, and that IP often was developed by third parties. But there are growing problems with that methodology, especially at advanced nodes where back-end issues and the impact of ‘shift left’…

Tipping the scale in favor of a massive on-premise compute farm is becoming more difficult.

The breadth of cloud capabilities and improvements in cost and licensing structures is prompting chipmakers to consider offloading at least some of their design work into the cloud.
Cloud is a viable business today for semiconductor design. Over the past decade, the interest in moving to cloud computing has grown from an idea that was fun to talk about — but…

At this year’s (virtual) functional design and verification conference, DVCon US 2022, the RISC-V Verification Interface (RVVI) was announced.

At this year’s (virtual) functional design and verification conference, DVCon US 2022, the RISC-V Verification Interface (RVVI) was announced by Imperas Software. The interface [specification] is available at github…

New open standard RISC-V Verification Interface (RVVI) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification

Oxford, United Kingdom – March 1st, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the official 1.0 release of the new RVVI (RISC-V…

The latest ImperasDV test suite for PMP covers the full envelope of configuration options

Oxford, United Kingdom – February 28th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the beta release of the ImperasDV architectural validation test suites for RISC-V Physical Memory Protection (PMP). The open standard ISA (Instruction Set Architecture) of…

Interest in this particular ISA is expanding, but the growth of other open-source hardware is less certain.

There is no disputing the excitement surround the introduction of the RISC-V processor architecture. Yet while many have called it a harbinger of a much broader open-source hardware movement, the reasons behind its success are not obvious, and the implications for an expansion of more open-source cores is far from certain…

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Chip design complexity is overwhelming them, and they are prone to errors. However, they’re still useful for some jobs.

Spreadsheets have been an invaluable engineering tool for many aspects of semiconductor design and verification, but their inability to handle complexity is squeezing them out of an increasing number of applications.

This is raising questions about whether they still have a role, and if so, how…