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Meetup: RISC-V DV: The Most Important Task

Imperas presentation on "RISC-V DV: The Most Important Task" by VP of Sales at Imperas, at the RISC-V virtual Meetup event held on July 22 2020.

Imperas are the guest host for the RISC-V Israel Meetup event and included talks by WD and Syntacore. The Imperas talk focused on the most critical design challenges for SoC adopting RISC-V and the latest updated on the RISC-V Processor DV.

 

This Meetup video can be viewed on YouTube here.

 

 

 

Comments

  • Nagra Kudelski

    Nagra, part of the Kudelski Group, a global leader in digital security and convergent media solutions for the delivery of digital and interactive content stated: "At NAGRA, we have adopted the Imperas virtual platform-based software development and test tools for our application and firmware teams. The simulator performance, and the tools for software analysis, have added significant value to our daily Agile Continuous Integration (CI) methodology. Our view is that software simulation is mandatory to reach metrics required for high quality secured products."

  • Hideki Sugimoto, CTO

    NSITEXE, Inc., a group company of DENSO Corporation

    The NSITEXE Akaria processors, developed with the use of Imperas RISC-V verification technology and the leading-edge SystemVerilog simulator and debug tools from Cadence, are targeted to address the high-performance requirements for AI and automotive requirements. The Akaria processors include the necessary features and quality to achieve the ISO 26262 ASIL D functional safety standard, in addition to being optimized and efficient processors for the next-generation embedded application.

    As the NSITEXE Akaria processors are adopted across a wide range of next-generation automotive, safety-critical, and embedded applications, the verification methodology with the support from Imperas and Cadence has been invaluable in achieving our quality goals and on-time development schedule.