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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Brief introduction to the 5 levels of RISC-V processor verification

 

RISC-V Summit 2021

Abstract:
The open RISC-V Instruction Set Architecture (ISA) is enabling a wide range of options on the design side, to completement this a number of options can be applied to the verification tasks, since a basic proof of concept prototype may not need all the quality checks as a high volume or high reliability application. This talk will review the 5 different simulation-based DV flows, ranging from simple signature-based comparisons for architectural validation to advanced ‘step-and-compare’ flows that support the most complex processors.

Speaker:     Kevin McDermott – Imperas Software 

The PDF of the slides used in this talk are available at this link

This RISC-V Summit 2021 presentation can be viewed on the RISC-V YouTube channel here.

 

 

 

Comments

  • Premal Buch, VP Software

    Altera

    Given the wide variety of customer applications for our SoC FPGAs, our software stacks require rigorous and comprehensive testing.  Imperas' M*SDK has proven to be an outstanding environment for the validation and analysis of operating systems, drivers and firmware. Verification using the Imperas solution not only accelerates software bug discovery, but also provides a rapid understanding of the root cause of problems.

  • Melaine Facon, Director of Codasip’s French Design Centre

    Codasip

    An open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects.

    With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.