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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Summit 2022: All Your CPUs Belong to Us

EETimes

 

In a recent guest editorial here on EE Times, legendary professor David Patterson wrote about busting the five myths around the RISC-V instruction set architecture (ISA). At the recent RISC-V Summit organized by RISC-V International, the consortium that manages and promotes the RISC-V Instruction Set Architecture (ISA), its president, Calista Redmond, had a far more blunt message: RISC-V is inevitable.
In fact, she said, RISC-V will eventually have the best CPUs, the best software running on them and the best ecosystem of any microprocessor core family. These are mighty strong words for a nascent ISA that is only about 10 years old and that competes with the far more established Arm and x86 ISAs. It almost sounded like the Borg from Star Trek when they say, “Resistance is futile”…

To read the full EE Times article by Kevin Krewell, click here.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Custom Instruction Flow Application Note

Comments

  • Michael Wittner, Managing Director

    Razorcat Development GmbH

    Over the past 20 years TESSY has become the established reference platform for automatic regression testing and software maintenance.

    In supporting the Imperas reference models and virtual platforms, our customers benefit from the quality reference models and flexibility to cover the configurations supported in deployed devices and plan for the next generation of hardware enhancements.

  • Rick O’Connor, President & CEO

    OpenHW Group

    The OpenHW Verification Task Group contributors are pioneers in the drive to advance the quality of open-source hardware IP ready for mainstream adoption – quality deliverables are the hallmark of any trusted IP provider, commercial or open source.

    OpenHW membership growth over the past three years is expanding the roadmap of IP core projects dramatically, with projects addressing the needs for application class devices supporting Linux, embedded security, and compute intensive applications with custom instructions. The RVVI open standard and flexible methodology significantly helps the OpenHW Verification Task Group members and contributors with efficient and quality verification for the full range of CORE-V IP projects.