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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Summit 2021 - SW Keynote talk: Is hardware/software co-design for applications now a reality with RISC-V?

Abstract:

RISC-V Vector instructions offer significant flexibility and options to configure a hardware accelerator for applications such as Datacenters and AI. Following initial cloud-based development with extensive real-world datasets, the migration to a hardware accelerator array with RISC-V vectors is redefining the software driven approach to hardware design.
This talk highlights SoC architectural exploration with multicore arrays and optimized RISC V processors to support early software development for vector accelerators. It introduces some of the challenges and discusses different approaches being adopted in the community/industry.

Co-Author:       Kevin McDermott – Imperas Software
Co-Author:       Simon Davidmann – Imperas Software

The video of this presentation is available at this link.
 

 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

ARM TrustZone Platform Modeling Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Kazutoshi Wakabayashi, Senior Manager

    Embedded Systems Solution Division, NEC

    OVP is widely used by our customers, who demanded the integration with CyberWorkBench. This integration significantly broadens CWB's HW/SW co-verification support. We were also very impressed with Imperas technical support helping us achieve this integration extremely quickly and efficiently.

  • Rick O’Connor, President & CEO

    OpenHW Group

    The defining goal of the OpenHW group is to deliver high quality open source IP cores, by leveraging the leading verification methodologies compatible with the established EDA commercial SoC design flows.

    To support our world class IP portfolio, the OpenHW working groups are enabling adoption with tools and software support for CORE-V processors. The Imperas contribution with the new free ISS, riscvOVPsimCOREV will be the foundation reference to all software tasks.