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Revolutionizing Embedded Software Development

RISC-V Summit 2021 - Demo Theatre DV talk: Brief introduction to the 5 levels of RISC-V processor verification

Abstract:

The open RISC-V Instruction Set Architecture (ISA) is enabling a wide range of options on the design side, to completement this a number of options can be applied to the verification tasks, since a basic proof of concept prototype may not need all the quality checks as a high volume or high reliability application. This talk will review the 5 different simulation-based DV flows, ranging from simple signature-based comparisons for architectural validation to advanced ‘step-and-compare’ flows that support the most complex processors.

Co-Author:       Kevin McDermott – Imperas Software
Co-Author:       Lee Moore – Imperas Software

The video of this presentation is available at this link.
 

 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Hideki Sugimoto, CTO

    NSITEXE, Inc.

    New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success.

    The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.

  • G. S. Madhusudan, CEO

    InCore

    RISC-V momentum and interest is wide-ranging across academic and industry. In providing support for the IIT Madras Shakti processors, InCore sees an increasing attention to test and verification that will be supported with riscvOVPsim.