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DVCon 2021 Slides on RISC-V Processor Verification: Case Study with NVIDIA Networking


The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. A key question is how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? This paper reports on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an experienced SoC design team, including the development of the reference model and the SystemVerilog and C encapsulation of the reference model, the step-and-compare flow used included co-debug, and the Specman-based verification environment.

Co-Author:       Adi Maymon – NVIDIA Networking
Co-Author:       Shay Harari – NVIDIA Networking
Co-Author:       Lee Moore – Imperas Software
Co-Author:       Larry Lapides – Imperas Software