Mind-boggling number of options emerge, but which is best often isn’t clear.
The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts.
For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes with huge financial risk and heightened responsibility over longer chip lifetimes. Up to and including the 28nm node, these kinds of decisions were defined by the ITRS roadmap and Moore’s Law. But as the power and performance benefits of scaling began diminishing, and the cost to design and manufacture three-dimensional transistors started trending upward, semiconductor economics began looking very different….
To read the full Semiconductor Engineering article by Ed Sperling, click here.