For a demo of how easy it is to download, and a quick walk through downloading and running the applications please watch the video.
Bill McSpadden, Principal VLSI Verification Engineer
The Imperas Golden RISC-V Reference Model helped us find many bugs in our cores.
However, the RISC-V architectural tests yielded no bugs, which is expected since the architectural tests are a subset of full verification.
Martin Baker, Senior Manager
Automotive Business Unit of Renesas Electronics America.
Imperas is launching some very interesting approaches to processor modeling and software testing. Historically processor models have been used in relatively small numbers, despite their enormous benefits. The Imperas business model has the potential to make processor modeling an affordable approach used widely across the industry.