New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success.
The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.
Professor Jong Tae Kim
Sungkyunkwan University, Seoul, South Korea - SKKU
Imperas OVP modeling and high-level simulation platforms unify both hardware and software development for multi-core designs, and are clearly the wave of the future. Access to the University Program allows my students access to advanced technologies essential to their future endeavors.