At each new process node, gates are free. That opens the door to a lot more IP blocks, and a lot of new challenges.

Driven by each successive generation of semiconductor manufacturing technology, complexity has reached dizzying levels. Every part of the design, verification and manufacturing is more complicated and intense the more transistors are able to be packed onto a die. For these reasons, the entire system must be taken into consideration as a whole…..

To read the article by Ann Mutschler, click…

These eight companies are developing their own RISC-V technologies and are committing to helping third parties do the same to help push adoption of the open-source chip architecture.

RISC-V (pronounced “risk five”), the open-source architecture for chip design, has been making a lot of noise in the past few years. The open source nature of RISC-V promises…

The road to optimized tradeoff automation is long. Changing attributes along the way can make it even more difficult.

Complexity challenges long-held assumptions. In the past, the semiconductor industry thought it understood performance/area tradeoffs, but over time it became clear this is not so simple. Measuring performance is no longer an absolute. Power has many dimensions including peak, average, total energy and heat, and power and function are tied together.

Design teams are now dealing with the implication of safety and security, which have considerable impact on power/…

Highlights of the inaugural Verification 3.0 Innovation Summit in Silicon Valley March 2019.

I’m that rare person, a native (even second generation) Californian, and grew up going to the Southern California beaches during the summers. I earned my Red Cross…

Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.

The open-standard RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the…

Experts at the Table: While attention is being paid to security in IoT devices, still more must be done.

Semiconductor Engineering sat down with Chris Jones, vice president of marketing at Codasip; Martin Croome, vice president of business development at GreenWaves Technologies; Kevin McDermott, vice president of marketing at Imperas; Scot Morrison, general manager, embedded platform technology at Mentor, a Siemens Business; Lauri Koskinen, CTO at Minima; and Mike Borza, principal security technologist at Synopsys. What follows are excerpts of that discussion…..

To read…

Bernard Murphy of SemiWiki is becoming more interested in developments in the RISC-V industry and has talked with Krste Asanovic of UCB and SiFive and with Imperas.

Compliance to the open-ISA standard is a big issue and Bernard talked with Kevin McDermott (VP Marketing at Imperas) to explore what is needed. Imperas' new free ISS, riscvOVPsim, a RISC-V compliance simulator is discussed.

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Imperas’ leading virtual platform simulation technology and embedded software analysis tools address the growth in new and emerging applications and increasing RISC-V adoption.

RISC-V Summit, Santa Clara, Calif., December 4, 2018 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced it is expanding its commercial channels to address the growth opportunities in the US market with…

Imperas leading virtual platform simulation technology combined with Valtrix leading verification technology for rigorous RISC-V Processor test developments, verification and compliance.

RISC-V Summit, Santa Clara, Calif., December 3, 2018 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the partnership with Valtrix Systems for…