Industry Events

DVCon, 3-6 March 2014, San Jose, California. Imperas present paper

DVCon is March 3-6 in San Jose, California.  Imperas will be presenting a paper titled “Learning From Advanced Hardware Verification for Hardware Dependent Software” as part of Session 3, at 9:30am Tuesday March 4th.  Here is the abstract: 

We present a new perspective for embedded software verification for generalized multicore processor platforms, somewhat analogous to simulation-centric hardware verification solutions. A spatial, temporal, and abstract multi-dimensional framework for software verification, profiling, analysis, and debug is proposed that leverages a specialized simulation core. The simulator enables key services for the verification solution while providing a degree of separation from both the hardware models and software under test, to ensure accurate behavioral representation, as well as customization and performance advantages.

This paper will discuss requirements for modern embedded software development and solutions utilized to date, before discussing this simulation-based solution and the dimensional framework layered above. We will also discuss two real life scenarios where the solution is utilized to affect.

Embedded World, 25-27 Feb 2014, Nuremberg, Germany. Imperas present paper, demos in partner booths

Embedded World is February 25-27 in Nuremberg, Germany.  Imperas will be presenting a paper titled “Customized, Intelligent Memory Access Monitoring for Reliable Asymmetric MultiProcessor System Development” in Session 23, Thursday at 14:00.  We will be available for demos of the Imperas simulation and software development, debug and test tools in the Altera booth Tuesday and Wednesday from 10:00-11:00 and 14:00-15:00, and Thursday from 10:00-11:00.  We will also be in the Imagination Technologies booth for demos of the Imperas tools for MIPS cores.

Here is a brief summary of the paper: 

The use of Asymmetric MultiProcessor (AMP) architectures is now widespread.  Two common implementations are Linux running on one core of a dual-core ARM Cortex-A9, with an RTOS running on the other, and SMP Linux running on the dual-core ARM Cortex-A9 and an RTOS or bare metal application running on another processor core, such as an Altera NIOS II. The reliability of such a system is highly dependent on the correct functioning of inter-core interaction with shared resources, which is often hard to verify. 

Imperas exhibit and demonstrate OVP at Embedded Technology show 2013, Nov 20-22, Yokohama, Japan

Embedded Technology 2013 ( http://www.embeddedtech.net/), November 20-22 in Yokohama, Japan, is the world’s largest  trade show and conference for embedded system designers and  managers.  The ET Conference & Exhibition introduces advanced technologies and solutions for emerging embedded applications, including digital consumer electronics,  automotive, wireless/ubiquitous computing and factory automation.

Imperas will again this year have a booth in the Venture Village area of the exhibit hall.  Imperas will demonstrate both OVP and Imperas tools, showing how virtual platform based technologies can provide benefits such as earlier software development (pre-silicon), and improved software testing (post-silicon).

Imperas and OVP to be demonstrated at ARM TechCon 2013, Oct 29-31, Silicon Valley

ARM Techcon 2013 ( http://www.armtechcon.com/), October 29-31 in Santa Clara, California, is the largest conference devoted to developers of ARM-based SoCs, software and systems, bringing together users, hardware and software vendors, ARM technologists and others in the ARM ecosystem.

Imperas at ARM Techcon:  Simon Davidmann will be participating on a panel session, and Imperas will have a booth in the exhibits. 

Panel title:  The Future of Collaborative Embedded SW Development, from the viewpoint of one Technology Chain Gang

Panel abstract:  The creation of a modern embedded processor platform solution requires components from a “technology chain” of contributing companies, including processor, platform, OS, IP, and tool providers.  The multicore architecture of these platforms, as well as the use of advanced processor features like TrustZone and virtualization, places a heavy demand on associated software development, requiring the entire technology chain to derive the most effective solution together.  Come hear these key members of one particular technology chain discuss their collaboration and the resulting evolution of next generation embedded software development methodologies.

Europractice Cadence and Imperas Virtual Prototyping Information Day, June 18, STFC Rutherford Appleton Laboratory, UK

The Microelectronics Support Centre at STFC Rutherford Appleton Laboratory is holding a free Virtual Prototyping information day with hands-on lab sessions, featuring Cadence VSP, Imperas, and the Xilinx Zynq™ Virtual Platform.  Imperas was recently added to the Europractice vendor list. 

The information day will include technical presentations from Imperas on OVP fast processor models and the Imperas M*SIM simulator, and Cadence on the Virtual System Platform (VSP) tool.  The Cadence virtual platform of the Xilinx Zynq device uses the Imperas OVP model of the dual core ARM Cortex™-A9 with the M*SIM simulator. 
A hands-on Imperas lab will allow attendees to explore the Imperas tools, by building a system using an OVP processor model, and modifying the processor instructions and extending the instruction set. 
This will be followed by a hands-on Cadence VSP lab which will use the Xilinx Zynq Virtual Platform as an example.  The lab will cover running and extending the Xilinx Zynq virtual platform (and this can be extended to any Virtual Platform), and carrying out Hardware and Software co-debug and development using Cadence VSP and the Cadence Incisive tools.

Design Automation Conference, June 2-6, Austin, Texas

If you are heading to the Design Automation Conference (DAC) in Austin, Texas, taking place June 2-6, Larry Lapides will be attending.  He would enjoy learning more about your virtual platform and software development requirements, as well as discussing the second generation Imperas products, including the Developer range of products and M*SDK.  Please contact sales@imperas.com to set up a meeting at DAC.

Visit us at the Multicore Developers Conference, May 21-22, Santa Clara, California

The Multicore Developers Conference (MDC) is focused on the discussion of both technical and business issues of designing and using multicore processors.   

Imperas at MDC:  Larry Lapides is presenting a paper, and Imperas will have a booth in the exhibits where we will be demonstrating solutions for software verification, analysis and profiling, ranging from code coverage and profiling to OS context switching analysis and fault injection.  Exhibit hours are Tuesday 12:30 – 2:30pm and 4:30 – 6:30pm, and Wednesday 12:15 – 2:15pm. 

Virtual Platform Based Software Debug & Testing for Multiprocessor/Multicore Systems, Larry Lapides, Wednesday May 22, 3:45pm

Abstract: 
As electronics systems get more complex, quality becomes a much bigger issue.  Solving the quality issue means improved debug and testing tools and methodologies.  Virtual platforms (software simulation) provide one approach, not only for functional software testing but also adding more advanced test and analysis capabilities like code coverage, profiling, fault injection and more.  Moreover, these tools can be implemented in a completely non-intrusive manner, adding validity to the testing methodology. 

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