Jingliang (Leo) Wang, Co-chair of the OpenHW Group Verification Task Group
Futurewei Technologies
The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.
The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.
Miroslav Popovic
Professor, University of Novi Sad, Serbia
Using Imperas and OVP in my course on Real-Time System Programming is an immense benefit. Embedded software development is a growing need worldwide, and advanced methodologies such as Imperas delivers are required for accelerated coding and quality.