The new scalar cryptography extension for RISC-V is designed to be lightweight and to be suitable for 32- and 64-bit base architectures, from embedded, IoT class cores to large, application class cores.
The working group coordinates the member driven contributions and we welcome the Imperas Crypto tests to support the early implementors and adopters.
Simon Davidmann, CEO
Imperas Software
Processor verification is challenging, and yet critical to RISC-V adoption.
ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.