Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Silicon Laboratories
Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.
Gunar Schirner
Associate Professor, Northeastern University, Boston, USA
I find Imperas tools and models invaluable for my research and my course, High Level Design of Hardware Software Systems. My students can now explore and command state-of-the-art prototyping technology for complex systems.