Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Silicon Laboratories
Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.
Guy Rabbat, President and CEO
Ashling Systems Corporation
Our integration with Imperas brings Ashling closer to our vision to become the provider of a complete RISC-V turnkey solution.