Steve Richmond, Co-chair of the OpenHW Group Verification Task Group
Silicon Laboratories
Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.
The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.
Shoi Egawa
CEO of SELTECH Corporation
Imperas enables SELTECH to create new value for our customers by reducing time and cost-to-market, while improving their overall system performance. Our work with market leaders including Imperas and Imagination will help us continue to strengthen our position across the Japanese electronics market and beyond.