CTO Bluespec Inc. and Chair of RISC-V Formal Task Group
The RISC-V ISA Formal Spec Task Group will produce a Formal Specification for the RISC-V ISA. We see the introduction of riscvOVPsim as an excellent reference platform to test and verify with.
Krystian Bacławski, Professor
Institute of Computer Science at University of Wroclaw
OVPsim beats QEMU in fidelity in CPU simulation - its determinism and speed were pretty impressive. OVPsim configurability is a big advantage as well. We were able to configure low-level CPU features, thanks to comprehensive documentation. I was also enthusiastic about the machine description file. It was easy to connect a missing interrupt signal we needed.