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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Imperas Software and Cadence System Development Suite

Simon Davidmann, President and CEO of Imperas Software highlights how the partnership with Cadence, leveraging the Cadence System Development Suite provides a solution to help make customers more efficient, save development costs and get products to market faster.

Comments

  • Chuanhua Chang, Chair of RISC-V International P Extension Task Group

    Andes Technology Corp.

    Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA.

    The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.

  • Alexander Redkin, CEO

    Syntacore

    As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.