Chuanhua Chang, Chair of RISC-V International P Extension Task Group
Andes Technology Corp.
Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA.
The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.
Krishna Raghavan, President
MIPS IP Licensing, Wave Computing
The Imperas simulation and modeling technology has been a reliable and high-quality testing model used internally by the MIPS engineering team for many years. We are delighted to partner with Imperas to make this industrial-grade simulation technology available to support the MIPS Open program and further the momentum around open hardware development.