As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.
Martin Baker, Senior Manager
Automotive Business Unit of Renesas Electronics America.
Imperas is launching some very interesting approaches to processor modeling and software testing. Historically processor models have been used in relatively small numbers, despite their enormous benefits. The Imperas business model has the potential to make processor modeling an affordable approach used widely across the industry.