RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.
Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project
ETH Zurich