Processor verification is challenging, and yet critical to RISC-V adoption.
ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.
Stephan Werner
Karlsruhe Institute of Technology
M*SDK, the OVP APIs and the OVP library of models have been a great asset to the FlexTiles project, enabling us to quickly create a virtual platform for our advanced architecture. We were able to use the Imperas technology and tools to develop multiple demonstrations of the FlexTiles architecture, including multiple hardware configurations, the Network on Chip (NoC) developed in this project and the operating system and software tools for FlexTiles.