RISC-V is enabling a new wave of design innovation, and successful projects depend on quality processor IP and dependable design platforms that offer architecture exploration and early software development.
Having supported the NSITEXE team on the extensive internal RISC-V processor verification, as well as on the virtual platform development task for multiple projects, the support team at eSOL TRINITY is now able to assist developers as they build the next generation of SoC designs using the Imperas tools and reference models for the NSITEXE Akaria processors.
Sebastian Ahmed, Senior Director of R&D
Silicon Labs
Silicon Labs selected Imperas simulation tools and RISC-V models for our design verification (DV) flow because of the quality of the models and the ease of use of the Imperas environment.
The Imperas golden reference model of the RISC-V core and their experience with processor RTL DV flows were also critical to our decision.