News & Press Articles

FlexTiles Adaptive Multicore SoC Virtual Platform Now Available from Imperas

Imperas Technologies Used for FlexTiles Program

Oxford, United Kingdom, 2 June 2015 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, today announced that a virtual platform for the FlexTiles platform is now available, based on Imperas™ and Open Virtual Platforms™ (OVP™) simulators and models. 

The FlexTiles platform is a self-adaptive heterogeneous multicore 3D System-on-Chip (SoC) architecture developed by a consortium of universities, research institutes and commercial companies, with funding from the European Union under the Seventh Framework Programme. A major challenge in computing is to leverage multicore technology to develop energy-efficient high-performance systems. This is critical for embedded systems with a very limited energy budget, as well as for supercomputers in terms of sustainability. Moreover, the efficient programming of multicore architectures is critical, especially with more than a thousand cores per SoC predicted by 2020.  These challenges were the drivers for the FlexTiles project.

Recore Systems Selects Imperas for Virtual Platform Based Software Development Tools

Imperas Extendable Platform Kit Accelerates Development for Recore Many-Core Hardware and Software Program

Oxford, United Kingdom, 2 April 2015 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, announced that Recore Systems has selected Imperas for virtual platform based software development tools.  Recore is building a new many core hardware platform for various applications, including embedded vision.  Recore was able to get started quickly by using an Extendable Platform Kit™ (EPK™) from Imperas. 

The FlexaWare platform (www.flexaware.net), new from Recore Systems, is a many-core embedded system with three closely connected components: many-core hardware, a runtime (many-core) OS, and a software development environment. As the platform is built from the ground up, it is imperative to test important design concepts immediately in a simulation environment, to confirm that they function as expected.

Since time to market is crucial, Recore Systems searched for a simulation framework that could support design space exploration as well as software development and test.  Recore selected Imperas because of the nature of the components already on offer in the Imperas EPKs.

Imperas is founding member of prpl Foundation's Security Working Group

Founding members of the Security PEG include Broadcom, CUPP Computing, Elliptic Technologies, Ikanos, Imagination Technologies, Imperas Software, Ingenic, Kernkonzept, Lantiq (recently acquired by Intel), Qualcomm Atheros, Inc., Seltech, and others.

In March 2015, the prpl Foundation, an open-source non-profit foundation focused on enabling next-generation datacenter-to-device portable software and virtualized architectures, today announced the formal organization of its Security PEG (prpl Engineering Group). The formation of the Security PEG follows months of intensive planning by a subset of prpl members dedicated to defining an open security framework for deploying secured and authenticated virtualized services in the IoT and related emerging markets.

The new Security PEG will define a security roadmap to get from today’s software-virtualized solutions to full hardware supported virtualization, enabling multi-domain security across processors (CPUs, GPUs, NPUs), heterogeneous SoCs and systems built on these technologies including connected devices, routers and hubs. In addition, the Security PEG will define necessary open APIs (application programming interfaces) for various levels of the security stack.

Fast Processor Models of MIPS Warrior Cores Released by Imperas and Open Virtual Platforms

Imperas Virtual Platform Products Provide Interface to Imagination Codescape Debugger

Oxford, United Kingdom, 23 February 2015 - Imperas™ is releasing the Open Virtual Platforms™ (OVP™) Fast Processor Models for the MIPS Warrior P-class and M-class CPU IP cores from Imagination Technologies.  Example virtual platforms are also being released, as well as support for the cores in the Imperas M*SDK™ advanced software development tools.  In addition, the Imperas M*SDK and M*DEV™ products support the use of the Imagination Codescape Debugger for embedded software debug and development.

The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/MIPS.  The models of the P5600 and M51xx processor cores, as well as models of other MIPS processors, work with the Imperas and OVP simulators, including the QuantumLeap™ parallel simulation accelerator, and have shown exceptionally fast performance of hundreds of millions of instructions per second.

Magillem partnering with Imperas: Enabling IOT using virtual platforms

This week it was announced that Magillem has been working with Imperas on tools for Virtual Platforms.

Daniel Payne of SemiWiki covered it here at SemiWiki.

The X-Spec tool from Magillem will generate hardware and software code based on specifications, creating System C TLM code and embedded C code. Models come from Imperas using OVP technology.

The full press release can be found here on EDACafe.

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Extendable Platform Kits for MIPS Released by Imperas

Enabling quick start for developing and testing software

Oxford, United Kingdom, 20 November 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, announced the availability of Extendable Platform Kits™ (EPKs™) for MIPS CPU cores from Imagination Technologies.

These EPKs for MIPS, available for download from the Open Virtual Platforms™ (OVP™) website, are designed to provide a base for users to run high-speed simulations of MIPS-based SoCs and platforms on any suitable PC. They are based on the functionality of Imagination’s MIPS FPGA evaluation platforms, enabling anyone to simulate MIPS-based systems using Imagination’s reference platforms. EPKs provide a base for users to extend the functionality of the virtual platform, to closer reflect their own platform, by adding more component models, running different operating systems or adding additional applications.

Kyma Systems Selects Imperas Virtual Platform Tools for Hypervisor Development

Imperas M*SDK used for KVM development supporting MIPS hardware virtualization instructions

Oxford, United Kingdom, June 3rd, 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, announced today that Kyma Systems has been successfully using the Imperas M*SDK™ for virtual platform-based development of hypervisors.  M*SDK enabled porting of the KVM hypervisor to support Imagination Technologies' latest MIPS cores with virtualization extensions.  The OS- and CPU-aware tools included with M*SDK also enabled more comprehensive and faster testing of the hypervisor.     

Imperas Announces ARMv8 ISS and ARMv8 Platform Roadmap

Imperas ISS is fastest ARMv8 simulation available

Oxford, United Kingdom, May 6th, 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation and processor core models, has released an Instruction Set Simulator (ISS) for the ARMv8-A architecture.  In addition, Imperas announced its roadmap for products and virtual platforms supporting the ARMv8 family, including having two Extendable Platform Kits™ (EPKs™) available by the end of Q2. 

The ARMv8-A architecture currently has two core families, Cortex™-A53 and Cortex-A57.  The ARMv8-A architecture is ARM’s first 64-bit processor architecture, with initial licensees being primarily in the mobile and server market segments.  With a new architecture, new cores and, in the server space, new applications for ARM® cores, testing of the software becomes increasingly important.  With test suites typically consisting of hundreds or even thousands of tests, each of over 10 billion instructions, simulation speed is critical for robust and comprehensive testing of the software.

The Imperas simulation solutions together with the Imperas ARMv8 ISS and upcoming Imperas ARMv8 processor models provide the highest simulation performance available in the market.

Imperas Supports Imagination MIPS Cores With Fastest Ever Processor Model Simulation

QuantumLeap parallel simulation accelerator enables virtual platform performance of greater than 16 billion instructions per second, the fastest commercial solution available today

Oxford, United Kingdom, February 4th, 2014 - Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, has added support for models of Imagination Technologies’ MIPS processors to QuantumLeap™, a parallel simulation performance accelerator.

QuantumLeap leverages Imperas’ new synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core Personal Computer (PC) host machines.  The Imperas technology - simulation plus processor core models - provides the MIPS ecosystem with the fastest software simulation solution in the industry. 

Imperas Delivers QuantumLeap Simulation Synchronization – Industry's First Parallel Virtual Platform Simulator

Parallel synchronization technology augments existing high-performance simulator to accelerate virtual platforms beyond 16,000 MIPS, the fastest commercial solution available today

Oxford, United Kingdom, October 22nd, 2013—Imperas Software Ltd. (www.imperas.com), the leader in high-performance software simulation, has released QuantumLeap™, a parallel simulation performance accelerator. QuantumLeap leverages a new synchronization algorithm to provide the fastest virtual platform software execution speed available today on standard, multi-core Personal Computer (PC) host machines.

The execution performance of this new technology has been measured on average at 15 times faster than the nearest commercial solution using standard benchmarks.

Many current System-on-Chip (SoC) hardware platforms, for example mobile and server devices, incorporate multi-core embedded processors coupled with hardware accelerators, all executing in parallel. The performance of existing, single-threaded virtual platform simulators does not adequately scale for these SoCs, creating a barrier to efficient virtual platform-based software development.

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