For our SystemC training courses, we want the attendees to focus on building SystemC models, and how to use those models. By using OVP Fast Processor Models, which work easily in SystemC virtual platforms, students do not have to worry about processor models, and are able to get the most out of our courses. The OVP models work well in our SystemC environment and also with other SystemC tools. We are excited to be able to expand our design service offerings in virtual platforms to our customers.
Rick O’Connor, Executive Director
RISC-V Foundation
The free and open nature of the RISC-V ISA fosters unprecedented levels of processor innovation. To harness this design freedom, the ecosystem requires robust development tools and the assurance that verification test benches can be developed and validated on supplier-neutral platforms. Imperas’ new riscvOVPsim is an important suite of tools that addresses this challenge.