Comments
Richard Bohn, Engineering Director
Seagate TechnologyThe flexibility of RISC-V helps us address domain-specific requirements with custom processors that go beyond the roadmap of the mainstream IP providers.
Designing a high-performance RISC-V processor that achieved up to 3x the performance in critical workloads was no small feat. We needed to balance the features and options with the verification implications. The combined solution of Imperas golden reference models and Valtrix STING has helped us to achieve our verification and schedule goals.
Dr. Charlie Su, President and CTO
Andes Technology Corp.RISC-V represents the potential for innovation, and it is the implementation of great ideas that are really generating exceptional results.
To unlock such potentials, Andes provides the AndeSysC™ environment, an extensible and near-cycle accurate SystemC model library for all AndesCore®. SoC architects can use it to construct a SystemC based virtual platform for performance evaluation of critical code segment and hardware/software co-optimization. ACE technology helps users implement custom functions and instructions, and it directly connects to the AndeSysC™ environment. Now with the close integration with the Imperas fast reference models and tools, design teams can embark on architecture exploration with complete application software for the next generation of domain specific devices with a seamless path to ACE implementation.