Chuanhua Chang, Chair of RISC-V International P Extension Task Group
Andes Technology Corp.
Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA.
The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start - adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.
Róisín O’Keeffe, VP Global Business Development
Ashling Microsystems
Ashling takes great care in the integration and combinations of technologies for our tools to support software developers. The Imperas riscvOVPsimCOREV reference simulator provides the foundational reference that CORE-V IDE’s can be based on.