One aspect that all RISC-V processor designers agreed on, both commercial vendors and open-source developers, is that quality is the key to successful IP core adoption.
The OpenHW Group have supported the adoption of RVVI from its inception through the member contributors in the OpenHW Verification Task Group, and now welcome the new features and growing adoption by the commercial community.
Dr. Charlie Su, President and CTO
Andes Technology Corp.
RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.
The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.