Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Golden RISC-V Reference Model was used as the “go/no-go” model to determine the RTL correct behavior with any discrepancies, bugs or issues with the design, tests, specifications, or test bench.
Gerard Rauwerda, CTO
Recore Systems
Imperas allowed us to quickly add our own components and build the topologies which we wanted to test. We had our first demo up and running in 20 minutes, and it took us just a few days to build a reference hardware architecture based on components in the Extendable Platform Kit (EPK). Last but not least, after just a few months we could start playing with our own many-core operating system on our many-core hardware design. The ease of use of the EPK, together with excellent Imperas documentation and support, have kick-started our FlexaWare platform development.