The free and open nature of the RISC-V ISA fosters unprecedented levels of processor innovation. To harness this design freedom, the ecosystem requires robust development tools and the assurance that verification test benches can be developed and validated on supplier-neutral platforms. Imperas’ new riscvOVPsim is an important suite of tools that addresses this challenge.
Hideki Sugimoto, CTO
NSITEXE, Inc.
New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success.
The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.